With integrated circuit (IC) technology being scaled to ever smaller dimensions to achieve higher performance and integration levels, power dissipation has become an important consideration in modern VLSI (very large scale integrated) circuit designs. In one type of circuit design, for example, sets of transistors (e.g., field effect transistors (FETs)) are arranged in a pull-down and pull-up relationship, such as for implementing dynamic circuits that perform logic functions.
As transistor sizes scale down in such circuits, however, there tends to be increased leakage through pull-down transistors. The pull-down network includes transistors arranged to pull an output node from a first voltage to a second, lower voltage. A pull-up network is designed to maintain the output node at the first voltage by compensating for the leakage through the pull-down network. The increased leakage through the pull-down network generally requires an increase in the size of the pull-up transistor(s), which results in increased power consumption and reduced operating performance.